Current research in the field of PLA circuits is directed to increasing their operating speed. One solution adopted is to associate bipolar transistors with the field effect transistors of the logic network. This technology is currently known as BiMOS, or BiCMOS in the case of a CMOS environment (complementary MOS). In the conventional manner, a PLA circuit essentially comprises a matrix of logic products, or AND matrix, which receives the input signals of the PLA circuit, and a logical sum matrix or OR matrix, which receives the output signals of the AND matrix and furnishes the output signals of the PLA circuit. By a known method, each programming point of the AND matrix is embodied by a field effect transistor, mounted as noted above, while each programming point of the OR matrix is embodied by a bipolar transistor provided with a plurality of collectors, equal in number to the plurality of output lines of the PLA circuit, in accordance with IIL technology (integrated injection logic).
This BiMOS PLA circuit has the advantage of being highly integrated. Nevertheless, the bipolar transistors which assure maximum speed of the PLA circuit are concentrated exclusively in the output matrix of the PLA circuit, that is, the OR matrix. Furthermore, a static current is present in a circuit of the IIL type. The increase in speed of the BiMOS PLA circuit is thus improved only very slightly. Furthermore, the dimensioning of the field effect transistor in each programming point of the input matrix presents a difficult problem. In theory, rapid operation requires a large-sized field effect transistor. However, a large-sized transistor has an even higher capacitance. A matrix embodied by large field effect transistors would thus be a set of strong capacitors, mounted in parallel between ground and each input line, and between ground and each output line. Added together, these high capacitances would cause a major slowdown in the switching of the input lines and the discharging of the output lines. In conclusion, the presence of large field effect transistors in a programmable logic network means that they lose their speed and their large scale of integration. This explains why in practice a programmable logic network of the conventional type is embodied by small field effect transistors, which make its operation relatively slow, yet retain the advantage of large scale integration.